Synopsys synplify pro pro#
Synopsys synplify pro verification#
Synopsys synplify pro software#

Synopsys synplify pro software#

To improve productivity in implementing large-scale designs, the new Synplify software release expands on the tools' hierarchical design flow capability with a new GUI interface. Synplify Premier software also automates implementation of 1-hot safe FSM error detection circuitry, further increasing in-field system reliability of FPGA devices. The 2011.09 Synplify software release gives designers the ability to create designs that are resistant to single event upsets (SEUs) by including an option for designers to automatically preserve sequential logic. Customers designing with our FPGAs will also find Synplify Premier software's hierarchical-design flow and advanced debug features improve their productivity in creating large-scale designs.” “As Synopsys expands support for DesignWare, it enables designers prototyping SoCs to more easily integrate their key design functionality into their Xilinx devices. “Partnering with technology leaders like Synopsys enables us to deliver highly integrated design solutions to the benefit of our mutual customers,” said Tom Feist, senior marketing director, design methodology marketing at Xilinx. Synplify's enhanced hierarchical design flow, together with Quartus II Incremental Compilation feature, gives customers using our highest-density devices the ability to save hours per iteration by enabling quicker debug and validation of their design while preserving parts of the design that are already known to work.”

Synopsys synplify pro pro#

“The powerful combination of the Synplify Pro software with Altera's Quartus® II Place and Route software and our high-performance FPGA families gives designers an easy way to quickly divide and conquer their complex systems.

“The enhancements in the latest release of Synopsys' Synplify synthesis software enable designers using our Stratix FPGAs to quickly complete their complex designs,” said Phil Simpson, senior manager of software technical marketing at Altera. For ASIC prototypers, support for Synopsys DesignWare Library MacroCell IP has been added, broadening DesignWare IP support and improving compatibility with Design Compiler. Additionally, an enhanced interface for the tool allows designers to track progress and analyze synthesis results hierarchically.

The new Synplify tool release enables engineers to build higher reliability into their FPGA designs through a new feature that provides automated creation and preservation of error-correction logic, including safe finite-state machines (FSMs).

Synopsys synplify pro verification#

Synopsys, a world leader in software and IP used in the design, verification and manufacture of electronic components and systems, today announced availability of the latest release of its Synplify Pro and Synplify Premier FPGA synthesis tools. In about 10 minutes I have to race down to the airport to catch a plane, so I am just going to post this press release as it is…